Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manual do Utilizador descarregar pdf (Página 107)

PDI Description

Slave Controller – IP Core for Xilinx FPGAs III-95

10.3.8 Connection with 8 bit µControllers

If the ESC is connected to 8 bit µControllers, the BHE signal as well as the DATA[15:8] signals are not

used.

CS CS

ADR[15:0]

BUSY

ADR[15:0]

BUSY

DATA[15:8] (unused)

8 bit µController, async

EtherCAT device

IRQ IRQ

BHE (unused)

General purpose input EEPROM_Loaded

optional

DATA[7:0] DATA[7:0]

Figure 48: Connection with 8 bit µControllers (BHE and DATA[15:8] should not be left open)

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manual do Utilizador Página 107