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EtherCAT IP Core for Xilinx FPGAs

Slave Controller – EtherCAT IP Core Data Sheet Addendum 12

3.3.5 ISE/EDK/PlanAhead 14.7

3.3.5.1 ISE: Crash in libSecurity_FNP.dll

After installing both ISE 14.7 and Vivado 2014.1 on a Microsoft Windows 7 64 bit operating system, a crash occurred while synthesizing the EtherCAT IP Core using ISE 14.7. The crash was caused by libSecurity_FNP.dll. This issue is

approved by Xilinx, but there will not be any future version of ISE.

Solution

Refer to Answer Record 59851 for an ISE 14.7 patch.

3.3.5.2 ISE/EDK/PlanAhead: Additional BUFG inserted

Under certain circumstances, the tools insert additional BUFGs into the clock signals to the EtherCAT IP Core (CLK25, CLK100), or the BUFGs are not placed at optimal sites. This results in an error message suggesting to add a

CLOCK_DEDICATED_ROUTE=FALSE constraint to the clocks. This issue occurs especially when the MAP option “Global optimization” is different from OFF. This issue is reported to Xilinx and present at least until ISE 14.5.

Solution

Either set Global optimization to OFF or add the CLOCK_DEDICATED_ROUTE=FALSE constraint.

3.3.5.3 ISE/EDK/PlanAhead: CLOCK_DEDICATED_ROUTE=FALSE constraint required

The PDI_SPI_SEL, PDI_SPI_DI and MII_RX_CLK0/1/2 signals are used as clock inputs for a few registers at low speed. Since these signals are not placed on dedicated clock inputs – which is not required –, Xilinx ISE sometimes issues

an error, which needs to be suppressed.

Solution

Add an additional constraint for the signals causing the error message (or uncomment the appropriate lines in the example UCF files):

CLOCK_DEDICATED_ROUTE = FALSE

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