Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manual do Utilizador descarregar pdf (Página 112)

PDI Description

III-100 Slave Controller – IP Core for Xilinx FPGAs

10.2.5 Commands

The command CMD0 in the second address/command byte may be READ, READ with following Wait

State bytes, WRITE, NOP, or Address Extension. The command CMD1 in the third address/command

byte may have the same values:

Table 49: SPI commands CMD0 and CMD1

CMD[2]

CMD[1]

CMD[0]

Command

NOP (no operation)

reserved

Read

Read with following Wait State bytes

Write

reserved

Address Extension (3 address/command bytes)

reserved

10.2.6 Interrupt request register (AL Event register)

During the address phase, the SPI slave transmits the PDI interrupt request registers 0x0220-0x0221

(2 byte address mode), and additionally register 0x0222 for 3 byte addressing on SPI_DO (MISO):

Table 50: Interrupt request register transmission

Byte

2 Byte address mode

3 Byte address mode

SPI_DI

(MOSI)

SPI_DO

(MISO)

SPI_DI

(MOSI)

SPI_DO

(MISO)

A[12:5]

I0[7:0] interrupt request

A[12:5]

I0[7:0] interrupt request register

0x0220

A[4:0]

CMD0[2:0]

I1[7:0] interrupt request

A[4:0]

CMD0[2:0]

I1[7:0] interrupt request register

0x0221

(Data phase)

A[15:13]

CMD1[2:0]

I2[7:0] interrupt request register

0x0222

10.2.7 Write access

In the data phase of a write access, the SPI master sends the write data bytes to the SPI slave

(SPI_DI/MOSI). The write access is terminated by taking back SPI_SEL after the last byte. The

SPI_DO signal (MISO) is undetermined during the data phase of write accesses.

10.2.8 Read access

In the data phase of a read access, the SPI slave sends the read data bytes to the SPI master

(SPI_DO/MISO).

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