Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manual do Utilizador descarregar pdf (Página 140)

Electrical Specifications

III-128 Slave Controller – IP Core for Xilinx FPGAs

13 Electrical Specifications

Table 68: AC Characteristics

Symbol

Parameter

Min

Typ

Max

Units

CLK25

Clock source (CLK25) with initial

accuracy

25 MHz ± 25 ppm

Table 69: Forwarding Delays

Symbol

Parameter

Min

Average

Max

Units

PRELIMINARY TIMING

Diff

Average difference processing

delay minus forwarding delay

(without RX FIFO jitter)

MII port to MII port delay:

a) Through ECAT Processing Unit

(processing)

b) Alongside ECAT Processing Unit

(forwarding)

Conditions: FIFO size 7, no TX Shift

compensation or manual TX Shift

configuration with

MII_TX_SHIFT = 00

a) 300+x

b) 260+x

a) 320+x

b) 280+x

a) 340+x

b) 300+x

NOTE: Average timings are used for DC calculations.

EtherCAT IP Core: time depends on synthesis results

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