Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manual do Utilizador descarregar pdf (Página 54)

IP Core Configuration

III-42 Slave Controller – IP Core for Xilinx FPGAs

5.1.5 Register: Process Data Interface tab

Several interfaces between ESC and the application are available:

 Digital I/O

 8 Bit asynchronous µController

 16 Bit asynchronous µController

 SPI slave

 PLB v4.6 on-chip bus

 AXI4/AXI4 LITE on-chip bus

 General Purpose I/O

EtherCAT

Logic

PDI

SPI

Digital I/O

µC 8 Bit

PLB/

AXI

EtherCAT IP Core

Microblaze

RAM

…..

µC 16 BitPDI

FPGA

PHY

General

Purpose I/O

Figure 17: Available PDI Interfaces

The PDI can be selected from the pull down menu. After selection settings for the selected PDI are

shown and can be changed. If the EtherCAT IP Core is used in the EDK, only PLB and AXI on-chip

busses are selectable.

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manual do Utilizador Página 54