Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manual do Utilizador descarregar pdf (Página 77)

IP Core Signals

Slave Controller – IP Core for Xilinx FPGAs III-65

Condition

Name

Direction

Description

Port2 = MII

nMII_LINK2

INPUT

0: 100 Mbit/s (Full

Duplex) link at port 2

1: no link at port 2

MII_RX_CLK2

INPUT

Receive clock port 2

MII_RX_DV2

INPUT

Receive data valid port 2

MII_RX_DATA2[3:0]

INPUT

Receive data port 2

MII_RX_ERR2

INPUT

Receive error port 2

MII_TX_ENA2

OUTPUT

Transmit enable port 2

MII_TX_DATA2[3:0]

OUTPUT

Transmit data port 2

Port2 = MII and TX

Shift activated

MII_TX_CLK2

INPUT

Transmit clock port 2 for

automatic TX Shift

configuration. Set to 0 for

manual TX Shift

configuration.

MII_TX_SHIFT2[1:0]

INPUT

Manual TX shift

configuration port 2.

Additional TX signal delay:

00: 0 ns

01: 10 ns

10: 20 ns

11: 30 ns

1 2 ... 72 73 74 75 76 77 78 79 80 81 82 ... 143 144

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manual do Utilizador Página 77

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