
IP Core Signals
Slave Controller – IP Core for Xilinx FPGAs III-73
8.6.5 PLB Processor Local Bus
Table 32 lists the signals used with the PLB v4.6 PDI.
Table 32: PLB PDI
PLB data bus width (only 32
supported)
PLB bus clock period in ps (≤ 40,000)
PLB bus reset (replaces nRESET)
PLB upper address bus (not
supported)
PLB primary address valid
PLB secondary address valid
(ignored)
PLB secondary to primary read
request (ignored)
PLB secondary to primary write
request (ignored)
PDI_PLB_masterID
[0:C_SPLB_MID_WIDTH-1]
PDI_PLB_BE
(0:(C_SPLB_DWIDTH/8)-1)
PLB master data bus size (ignored)
PLB transfer size (must be 0000)
PLB transfer type (must be 0)
PDI_PLB_wrDBus
(0:C_SPLB_DWIDTH-1)
PLB burst write transfer (ignored)
PLB burst read transfer (ignored)
PLB pending write bus request
(ignored)
PLB pending read bus request
(ignored)
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