Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manual do Utilizador descarregar pdf (Página 133)

PDI Description

Slave Controller – IP Core for Xilinx FPGAs III-121

10.5 AXI4/AXI4 LITE On-Chip Bus

10.5.1 Interface

The AXI4 Slave PDI is selected during the IP Core configuration. The signals of the AXI4 interface

are

EtherCAT

IP core

CLK_PDI_EXT

Read address

channel

Read data

channel

Write address

channel

Write data

channel

Write response

channel

IRQ_MAIN

IRQ_DC_SYNC0/1

Figure 60: AXI4 signals

Table 61: AXI4 LITE signals

Signal

Directio

Description

Channel

Signal

polarity

PDI_AXI_ACLK

INPUT

AXI bus clock

PDI_AXI_AWADDR[15:0]

INPUT

Write address

WR addr.

PDI_AXI_AWPROT[2:0]

INPUT

Write protection type

WR addr.

PDI_AXI_AWREGION[3:0]

INPUT

Write region identifier

WR addr.

PDI_AXI_AWQOS[3:0]

INPUT

Write QoS identifier

WR addr.

PDI_AXI_AWVALID

INPUT

Write address valid

WR addr.

act. high

PDI_AXI_AWREADY

OUTPUT

Write address ready

WR addr.

act. high

PDI_AXI_WDATA

[PDI_EXT_BUS_WIDTH-1:0]

INPUT

Write data

WR data

PDI_AXI_WSTRB

[PDI_EXT_BUS_WIDTH/8-1:0]

INPUT

Write data byte enable

WR data

PDI_AXI_WVALID

INPUT

Write data valid

WR data

act. high

PDI_AXI_WREADY

OUTPUT

Write data ready

WR data

act. high

PDI_AXI_BRESP[1:0]

OUTPUT

Write response

WR resp.

PDI_AXI_BVALID

OUTPUT

Write response valid

WR resp.

act. high

PDI_AXI_BREADY

INPUT

Write response ready

WR resp.

act. high

PDI_AXI_ARADDR[15:0]

INPUT

Read address

RD addr.

The prefix `PDI_AXI_` or is added to the AXI interface signals for the IP Core interface.

1 2 ... 128 129 130 131 132 133 134 135 136 137 138 ... 143 144

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