Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manual do Utilizador Página 125

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PDI Description
Slave Controller IP Core for Xilinx FPGAs III-113
10.3.9 Timing Specification
Table 57: µController timing characteristics IP Core
Parameter
Min
Max
Comment
PRELIMINARY TIMING
t
CS_to_BUSY
x
10
BUSY driven and valid after CS assertion
t
ADR_BHE_setup
x
10
ADR and BHE valid before RD assertion
t
RD_to_DATA_driven
0 ns
11
DATA bus driven after RD assertion
t
RD_to_BUSY
0 ns
11
x
10
BUSY asserted after RD assertion
t
read
External read time (RD assertion to BUSY
deassertion) with normal read busy output
(0x0152[0]). Additional 20 ns if delayed read
busy output is configured.
a) t
read_int
11
a) without preceding write access or
t
WR_to_RD
t
write_int
or configuration: write after
falling edge of WR
b) t
read_int
+ t
write_int
-t
WR_to_RD
11
b) with preceding write access and
t
WR_to_RD
< t
write_int
c) 245 ns
11
c) 8 bit access, absolute worst case with
preceding write access (t
WR_to_RD
=min
,
t
write_int
=max)
d) 285 ns
11
d) 16 bit access, absolute worst case with
preceding write access (t
WR_to_RD
=min
,
t
write_int
=max)
t
read_int
a) 110 ns
11
b) 150 ns
11
a) 150 ns
11
b) 190 ns
11
Internal read time
a) 8 bit access
b) 16 bit access
t
BUSY_to_DATA_valid
a) x
10
-5 ns
b) x
10
-20 ns
DATA bus valid after device BUSY is
deasserted
a) normal read busy output
b) delayed read busy output
t
ADR_BHE_to_DATA_invalid
0 ns
11
DATA invalid after ADR or BHE change
t
CS_RD_to_DATA_release
0 ns
11
x
10
DATA bus released after CS deassertion or
RD deassertion
t
CS_to_BUSY_release
0 ns
11
x
10
BUSY released after CS deassertion
t
CS_delay
0 ns
11
Delay between CS deassertion an assertion
t
RD_delay
x
10
Delay between RD deassertion and
assertion
t
ADR_BHE_DATA_setup
x
10
ADR, BHE and Write DATA valid before WR
deassertion
t
ADR_BHE_DATA_hold
x
10
ADR, BHE and Write DATA valid after WR
deassertion
t
WR_active
x
10
WR assertion time
10
EtherCAT IP Core: time depends on synthesis results
11
EtherCAT IP Core: time depends on synthesis results, specified value has to be met anyway
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