Beckhoff EtherCAT Registers Section II Manual do Utilizador

Version 2.7 Date: 2013-07-01 Hardware Data Sheet Section II Slave Controller Section I – Technology (Online at http://www.beckh

TABLES II-X Slave Controller – Register Description Table 61: Register Watchdog Counter Process Data (0x0442) ...

TABLES Slave Controller – Register Description II-XI Table 123: Register Latch0 Time Positive Edge (0x09B0:0x09B3 [0x09B0:0x09B7])...

ABBREVIATIONS II-XII Slave Controller – Register Description ABBREVIATIONS ADR Address AL Application Layer APRW Auto Increment Physical ReadWrite B

Address Space Overview Slave Controller – Register Description II-1 1 Address Space Overview An EtherCAT Slave Controller (ESC) has an address s

Address Space Overview II-2 Slave Controller – Register Description Address1 Length (Byte) Description Interrupts 0x0200:0x0201 2 ECAT Event Mask

Address Space Overview Slave Controller – Register Description II-3 Address1 Length (Byte) Description 0x0800:0x087F 16x8 SyncManager[15:0] +0x0:

Address Space Overview II-4 Slave Controller – Register Description Address1 Length (Byte) Description DC – SyncManager Event Times 0x09F0:0x09F3

Address Space Overview Slave Controller – Register Description II-5 1.1 Scope of Section II Section II contains detailed information about all E

Address Space Overview II-6 Slave Controller – Register Description 1.3 ESC Availability Tab Legend The availability of registers and exceptions fo

ESC Register Availability Slave Controller – Register Description II-7 2 ESC Register Availability Table 2: ESC Register Availability Address Le

DOCUMENT ORGANIZATION II-II Slave Controller – Register Description DOCUMENT ORGANIZATION The Beckhoff EtherCAT Slave Controller (ESC) documentation

ESC Register Availability II-8 Slave Controller – Register Description Address Length (Byte) Description ET1200 ET1100 IP Core V3.0.2/ V3.00c ESC20

ESC Register Availability Slave Controller – Register Description II-9 Address Length (Byte) Description ET1200 ET1100 IP Core V3.0.2/ V3.00c ESC

Type (0x0000) II-10 Slave Controller – Register Description 3 Register description 3.1 Type (0x0000) Table 4: Register Type (0x0000) ESC20 ET11

SyncManagers supported (0x0005) Slave Controller – Register Description II-11 3.5 SyncManagers supported (0x0005) Table 8: Register SyncManagers

ESC Features supported (0x0008:0x0009) II-12 Slave Controller – Register Description 3.8 ESC Features supported (0x0008:0x0009) Table 11: Regist

Configured Station Address (0x0010:0x0011) Slave Controller – Register Description II-13 3.9 Configured Station Address (0x0010:0x0011) Table 12

ESC Write Enable (0x0030) II-14 Slave Controller – Register Description 3.13 ESC Write Enable (0x0030) Table 16: Register ESC Write Enable (0x00

ESC Reset ECAT (0x0040) Slave Controller – Register Description II-15 3.15 ESC Reset ECAT (0x0040) Table 18: Register ESC Reset ECAT (0x0040) ES

ESC DL Control (0x0100:0x0103) II-16 Slave Controller – Register Description 3.17 ESC DL Control (0x0100:0x0103) Table 20: Register ESC DL Contr

ESC DL Control (0x0100:0x0103) Slave Controller – Register Description II-17 Bit Description ECAT PDI Reset Value 15:14 Loop Port 3: 00: Auto 01

DOCUMENT HISTORY Slave Controller – Register Description II-III DOCUMENT HISTORY Version Comment 1.0 Initial release 1.1  Latch0/1 state regist

Physical Read/Write Offset (0x0108:0x0109) II-18 Slave Controller – Register Description 3.18 Physical Read/Write Offset (0x0108:0x0109) Table 2

ESC DL Status (0x0110:0x0111) Slave Controller – Register Description II-19 3.19 ESC DL Status (0x0110:0x0111) Table 22: Register ESC DL Status

ESC DL Status (0x0110:0x0111) II-20 Slave Controller – Register Description Bit Description ECAT PDI Reset Value 12 Loop Port 2: 0: Open 1: Close

AL Control (0x0120:0x0121) Slave Controller – Register Description II-21 3.20 AL Control (0x0120:0x0121) Table 24: Register AL Control (0x0120:0

AL Status (0x0130:0x0131) II-22 Slave Controller – Register Description 3.21 AL Status (0x0130:0x0131) Table 25: Register AL Status (0x0130:0x01

RUN LED Override (0x0138) Slave Controller – Register Description II-23 3.23 RUN LED Override (0x0138) Table 27: Register RUN LED Override (0x01

PDI Control (0x0140) II-24 Slave Controller – Register Description 3.25 PDI Control (0x0140) Table 29: Register PDI Control (0x0140) ESC20 ET110

ESC Configuration (0x0141) Slave Controller – Register Description II-25 3.26 ESC Configuration (0x0141) Table 30: Register ESC Configuration (0

PDI Information (0x014E:0x014F) II-26 Slave Controller – Register Description 3.27 PDI Information (0x014E:0x014F) Table 31: Register PDI Inform

PDI Configuration (0x0150:0x0153) Slave Controller – Register Description II-27 3.28 PDI Configuration (0x0150:0x0153) The PDI configuration reg

DOCUMENT HISTORY II-IV Slave Controller – Register Description Version Comment 1.6  EEPROM Control/Status register (0x0502:0x0503): Error bit descr

PDI Configuration (0x0150:0x0153) II-28 Slave Controller – Register Description 3.28.1 PDI Digital I/O configuration Table 33: Register PDI Digi

PDI Configuration (0x0150:0x0153) Slave Controller – Register Description II-29 Table 34: Register PDI Digital I/O extended configuration (0x0152

PDI Configuration (0x0150:0x0153) II-30 Slave Controller – Register Description 3.28.2 PDI SPI Slave Configuration Table 35: Register PDI SPI Sl

PDI Configuration (0x0150:0x0153) Slave Controller – Register Description II-31 3.28.3 PDI 8/16Bit asynchronous Microcontroller configuration Ta

PDI Configuration (0x0150:0x0153) II-32 Slave Controller – Register Description 3.28.4 PDI 8/16Bit synchronous Microcontroller configuration Tab

PDI Configuration (0x0150:0x0153) Slave Controller – Register Description II-33 Table 40: Register PDI Synchronous Microcontroller extended Confi

PDI Configuration (0x0150:0x0153) II-34 Slave Controller – Register Description 3.28.5 EtherCAT Bridge (port 3) Table 41: Register EtherCAT Brid

PDI Configuration (0x0150:0x0153) Slave Controller – Register Description II-35 3.28.6 PDI On-chip bus configuration Table 43: Register PDI On-c

PDI Configuration (0x0150:0x0153) II-36 Slave Controller – Register Description 3.28.7 Sync/Latch[1:0] PDI Configuration Table 45: Register Sync

ECAT Event Mask (0x0200:0x0201) Slave Controller – Register Description II-37 3.29 ECAT Event Mask (0x0200:0x0201) Table 46: Register ECAT Event

DOCUMENT HISTORY Slave Controller – Register Description II-V Version Comment 2.0  DC SYNC Activation register (0x0981.6): bit polarity correct

ECAT Event Request (0x0210:0x0211) II-38 Slave Controller – Register Description 3.31 ECAT Event Request (0x0210:0x0211) Table 48: Register ECAT

AL Event Request (0x0220:0x0223) Slave Controller – Register Description II-39 3.32 AL Event Request (0x0220:0x0223) Table 49: Register AL Event

AL Event Request (0x0220:0x0223) II-40 Slave Controller – Register Description Bit Description ECAT PDI Reset Value 8 9 …. 23 SyncManager in

RX Error Counter (0x0300:0x0307) Slave Controller – Register Description II-41 3.33 RX Error Counter (0x0300:0x0307) Errors are only counted if

PDI Error Counter (0x030D) II-42 Slave Controller – Register Description 3.36 PDI Error Counter (0x030D) Table 53: Register PDI Error Counter (0

Lost Link Counter (0x0310:0x0313) Slave Controller – Register Description II-43 3.38 Lost Link Counter (0x0310:0x0313) Table 56: Register Lost L

Watchdog Divider (0x0400:0x0401) II-44 Slave Controller – Register Description 3.39 Watchdog Divider (0x0400:0x0401) Table 57: Register Watchdog

Watchdog Status Process Data (0x0440:0x0441) Slave Controller – Register Description II-45 3.42 Watchdog Status Process Data (0x0440:0x0441) Tab

SII EEPROM Interface (0x0500:0x050F) II-46 Slave Controller – Register Description 3.45 SII EEPROM Interface (0x0500:0x050F) Table 63: SII EEPRO

SII EEPROM Interface (0x0500:0x050F) Slave Controller – Register Description II-47 Table 66: Register EEPROM Control/Status (0x0502:0x0503) ESC20

CONTENTS II-VI Slave Controller – Register Description CONTENTS 1 Address Space Overview 1 1.1 Scope of Section II 5 1.2 Reserved Registers/Rese

SII EEPROM Interface (0x0500:0x050F) II-48 Slave Controller – Register Description NOTE: r/(w): write access depends upon the assignment of the E

SII EEPROM Interface (0x0500:0x050F) Slave Controller – Register Description II-49 3.45.1 EEPROM emulation with IP Core Write access to EEPROM D

MII Management Interface (0x0510:0x0515) II-50 Slave Controller – Register Description 3.46 MII Management Interface (0x0510:0x0515) Table 70: M

MII Management Interface (0x0510:0x0515) Slave Controller – Register Description II-51 Table 71: Register MII Management Control/Status (0x0510:0

MII Management Interface (0x0510:0x0515) II-52 Slave Controller – Register Description Table 72: Register PHY Address (0x0512) ESC20 ET1100 ET120

MII Management Interface (0x0510:0x0515) Slave Controller – Register Description II-53 Table 76: Register MII Management PDI Access State (0x0517

FMMU (0x0600:0x06FF) II-54 Slave Controller – Register Description 3.47 FMMU (0x0600:0x06FF) Each FMMU entry is described in 16 Bytes from 0x060

FMMU (0x0600:0x06FF) Slave Controller – Register Description II-55 Table 83: Register Physical Start address FMMU y (0x06y8-0x06y9) ESC20 ET1100

SyncManager (0x0800:0x087F) II-56 Slave Controller – Register Description 3.48 SyncManager (0x0800:0x087F) SyncManager registers are mapped from

SyncManager (0x0800:0x087F) Slave Controller – Register Description II-57 Table 91: Register Control Register SyncManager y (0x0804+y*8) ESC20 ET

CONTENTS Slave Controller – Register Description II-VII 3.28.6 PDI On-chip bus configuration 35 3.28.7 Sync/Latch[1:0] PDI Configuration 36 3

SyncManager (0x0800:0x087F) II-58 Slave Controller – Register Description Table 92: Register Status Register SyncManager y (0x0805+y*8) ESC20 ET1

SyncManager (0x0800:0x087F) Slave Controller – Register Description II-59 Table 93: Register Activate SyncManager y (0x0806+y*8) ESC20 ET1100 ET1

SyncManager (0x0800:0x087F) II-60 Slave Controller – Register Description Table 94: Register PDI Control SyncManager y (0x0807+y*8) ESC20 ET1100

Distributed Clocks (0x0900:0x09FF) Slave Controller – Register Description II-61 3.49 Distributed Clocks (0x0900:0x09FF) 3.49.1 Receive Times T

Distributed Clocks (0x0900:0x09FF) II-62 Slave Controller – Register Description Table 98: Register Receive Time Port 3 (0x090C:0x090F) ESC20 ET1

Distributed Clocks (0x0900:0x09FF) Slave Controller – Register Description II-63 3.49.2 Time Loop Control Unit Time Loop Control unit is usually

Distributed Clocks (0x0900:0x09FF) II-64 Slave Controller – Register Description Table 102: Register System Time Delay (0x0928:0x092B) ESC20 ET11

Distributed Clocks (0x0900:0x09FF) Slave Controller – Register Description II-65 Table 106: Register System Time Difference Filter Depth (0x0934)

Distributed Clocks (0x0900:0x09FF) II-66 Slave Controller – Register Description Table 108: Register Receive Time Latch Mode (0x0936) ESC20 ET110

Distributed Clocks (0x0900:0x09FF) Slave Controller – Register Description II-67 3.49.3 Cyclic Unit Control Table 109: Register Cyclic Unit Cont

CONTENTS II-VIII Slave Controller – Register Description 4 Process Data RAM (0x1000:0xFFFF) 85 4.1 PDI Digital I/O Input Data (0x1000:0x1003) 85

Distributed Clocks (0x0900:0x09FF) II-68 Slave Controller – Register Description 3.49.4 SYNC Out Unit Table 110: Register Activation register (0

Distributed Clocks (0x0900:0x09FF) Slave Controller – Register Description II-69 Table 112: Register Activation Status (0x0984) ESC20 ET1100 ET12

Distributed Clocks (0x0900:0x09FF) II-70 Slave Controller – Register Description Table 115: Register Start Time Cyclic Operation (0x0990:0x0993 [

Distributed Clocks (0x0900:0x09FF) Slave Controller – Register Description II-71 3.49.5 Latch In unit Table 119: Register Latch0 Control (0x09A8

Distributed Clocks (0x0900:0x09FF) II-72 Slave Controller – Register Description Table 121: Register Latch0 Status (0x09AE) ESC20 ET1100 ET1200 I

Distributed Clocks (0x0900:0x09FF) Slave Controller – Register Description II-73 Table 123: Register Latch0 Time Positive Edge (0x09B0:0x09B3 [0x

Distributed Clocks (0x0900:0x09FF) II-74 Slave Controller – Register Description Table 125: Register Latch1 Time Positive Edge (0x09C0:0x09C3 [0x

Distributed Clocks (0x0900:0x09FF) Slave Controller – Register Description II-75 3.49.6 SyncManager Event Times Table 127: Register EtherCAT Buf

ESC specific registers (0x0E00:0x0EFF) II-76 Slave Controller – Register Description 3.50 ESC specific registers (0x0E00:0x0EFF) 3.50.1 Power-O

ESC specific registers (0x0E00:0x0EFF) Slave Controller – Register Description II-77 3.50.2 Power-On Values ET1100 Table 131: Register Power-On

TABLES Slave Controller – Register Description II-IX TABLES Table 1: ESC address space ...

ESC specific registers (0x0E00:0x0EFF) II-78 Slave Controller – Register Description 3.50.3 IP Core Table 132: Register Product ID (0x0E00:0x0E0

ESC specific registers (0x0E00:0x0EFF) Slave Controller – Register Description II-79 3.50.4 ESC20 Table 134: Register FPGA Update (0x0E00:0x0EFF

Digital I/O Output Data (0x0F00:0x0F03) II-80 Slave Controller – Register Description 3.51 Digital I/O Output Data (0x0F00:0x0F03) Table 135: Re

User RAM (0x0F80:0x0FFF) Slave Controller – Register Description II-81 3.54 User RAM (0x0F80:0x0FFF) Table 138: User RAM (0x0F80:0x0FFF) ESC20 E

User RAM (0x0F80:0x0FFF) II-82 Slave Controller – Register Description Addr. Bit Feat. Description Reset Value 0F84 0 24 Link/Activity LED 1 1 25

User RAM (0x0F80:0x0FFF) Slave Controller – Register Description II-83 Addr. Bit Feat. Description Reset Value 0F89 0 64 Reserved 0 1 65 Reserved

User RAM (0x0F80:0x0FFF) II-84 Slave Controller – Register Description Addr. Bit Feat. Description Reset Value 0F90 0 120 Reserved 0 1 121 Reserv

Process Data RAM (0x1000:0xFFFF) Slave Controller – Register Description II-85 4 Process Data RAM (0x1000:0xFFFF) 4.1 PDI Digital I/O Input Dat

Appendix II-86 Slave Controller – Register Description 5 Appendix 5.1 Support and Service Beckhoff and their partners around the world offer c