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Distributed Clocks (0x0900:0x09FF)

II-68 Slave Controller – Register Description

3.49.4 SYNC Out Unit

Table 110: Register Activation register (0x0981)

ESC20

ET1100

ET1200

IP Core

[7:3]

V2.2.0/

V2.02a

Bit

Description

ECAT

PDI

Reset Value

Sync Out Unit activation:

0: Deactivated

1: Activated

r/(w)

SYNC0 generation:

0: Deactivated

1: SYNC0 pulse is generated

r/(w)

SYNC1 generation:

0: Deactivated

1: SYNC1 pulse is generated

r/(w)

Auto-activation by writing Start Time Cyclic

Operation (0x0990:0x0997):

0: Disabled

1: Auto-activation enabled. 0x0981.0 is set

automatically after Start Time is written.

r/(w)

Extension of Start Time Cyclic Operation

(0x0990:0x0993):

0: No extension

1: Extend 32 bit written Start Time to 64 bit

r/(w)

Start Time plausibility check:

0: Disabled. SyncSignal generation if Start

Time is reached.

1: Immediate SyncSignal generation if

Start Time is outside near future (see

0x0981.6)

r/(w)

Near future configuration (approx.):

0: ½ DC width future (2

ns or 2

ns)

1: ~2.1 sec. future (2

ns)

r/(w)

SyncSignal debug pulse (Vasily bit):

0: Deactivated

1: Immediately generate one ping only on

SYNC0-1 according to 0x0981[2:1] for

debugging

This bit is self-clearing, always read 0.

r/(w)

NOTE: Write to this register depends upon setting of 0x0980.0.

Table 111: Register Pulse Length of SyncSignals (0x0982:0x983)

ESC20

ET1100

ET1200

IP Core

Bit

Description

ECAT

PDI

Reset Value

15:0

Pulse length of SyncSignals (in Units of

10ns)

0: Acknowledge mode: SyncSignal will be

cleared by reading SYNC[1:0] Status

r/-

IP Core: Depends on

configuration

Others: 0, later

EEPROM ADR 0x0002

1 2 ... 75 76 77 78 79 80 81 82 83 84 85 ... 97 98

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