
MII Management Interface (0x0510:0x0515)
II-52 Slave Controller – Register Description
Table 72: Register PHY Address (0x0512)
Show configured PHY address of port 0-3 in
register 0x0510[7:3]. Select port x with bits
[4:0] of this register (valid values are 0-3):
0: Show address of port 0 (offset)
1: Show individual address of port x
NOTE: r/ (w): write access depends on assignment of MI (ECAT/PDI). Write access is generally blocked if
Management interface is busy (0x0510.15=1).
Table 73: Register PHY Register Address (0x0513)
Address of PHY Register that shall be
read/written
NOTE: r/ (w): write access depends on assignment of MI (ECAT/PDI). Write access is generally blocked if
Management interface is busy (0x0510.15=1).
Table 74: Register PHY Data (0x0514:0x0515)
NOTE: r/ (w): write access depends on assignment of MI (ECAT/PDI). Access is generally blocked if Management
interface is busy (0x0510.15=1).
Table 75: Register MII Management ECAT Access State (0x0516)
Access to MII management:
0: ECAT enables PDI takeover of MII
management control
1: ECAT claims exclusive access to MII
management
NOTE: r/ (w): write access is only possible if 0x0517.0=0.
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