
FMMU (0x0600:0x06FF)
Slave Controller – Register Description II-55
Table 83: Register Physical Start address FMMU y (0x06y8-0x06y9)
Physical Start Address (mapped to logical
Start address)
Table 84: Register Physical Start bit FMMU y (0x06yA)
Physical starting bit as target of logical start
bit mapping (bits are counted from least
significant bit (=0) to most significant bit(=7)
Table 85: Register Type FMMU y (0x06yB)
0: Ignore mapping for read accesses
1: Use mapping for read accesses
0: Ignore mapping for write accesses
1: Use mapping for write accesses
Table 86: Register Activate FMMU y (0x06yC)
0: FMMU deactivated
1: FMMU activated. FMMU checks logical
addressed blocks to be mapped
according to mapping configured
Table 87: Register Reserved FMMU y (0x06yD:0x06yF)
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