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MII Management Interface (0x0510:0x0515)

Slave Controller – Register Description II-53

Table 76: Register MII Management PDI Access State (0x0517)

ESC20

ET1100

ET1200

IP Core

V2.0.0/

V2.00a

Bit

Description

ECAT

PDI

Reset Value

Access to MII management:

0: ECAT has access to MII management

1: PDI has access to MII management

r/-

r/(w)

Force PDI Access State:

0: Do not change Bit 517.0

1: Reset Bit 517.0 to 0

r/w

r/-

7:2

Reserved, write 0

r/-

NOTE: r/ (w): assigning access to PDI (bit 0 = 1) is only possible if 0x0516.0=0 and 0x0517.1=0, and if the SII

EEPROM is loaded (0x0110[0]=1).

Table 77: Register PHY Port y (port number y=0 to 3) Status (0x0518+y)

ESC20

ET1100

ET1200

IP Core

V2.0.0/

V2.00a;

[5]

V2.0.2/

V2.02a

Bit

Description

ECAT

PDI

Reset Value

Physical link status (PHY status register 1.2):

0: No physical link

1: Physical link detected

r/-

Link status (100 Mbit/s, Full Duplex,

Autonegotiation):

0: No link

1: Link detected

r/-

Link status error:

0: No error

1: Link error, link inhibited

r/-

Read error:

0: No read error occurred

1: A read error has occurred

Cleared by writing any value to at least one

of the PHY Status Port y registers.

r/(w/clr)

Link partner error:

0: No error detected

1: Link partner error

r/-

PHY configuration updated:

0: No update

1: PHY configuration was updated

Cleared by writing any value to at least one

of the PHY Status Port y registers.

r/(w/clr)

7:6

Reserved

r/-

NOTE: r/ (w): write access depends on assignment of MI (ECAT/PDI).

1 2 ... 60 61 62 63 64 65 66 67 68 69 70 ... 97 98

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