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Distributed Clocks (0x0900:0x09FF)

Slave Controller – Register Description II-75

3.49.6 SyncManager Event Times

Table 127: Register EtherCAT Buffer Change Event Time (0x09F0:0x09F3)

ESC20

ET1100

ET1200

IP Core

Bit

Description

ECAT

PDI

Reset Value

31:0

of the frame which causes at least one

SyncManager to assert an ECAT event

r/-

NOTE: Register bits [31:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which

guarantees reading a consistent value.

Table 128: Register PDI Buffer Start Event Time (0x09F8:0x09FB)

ESC20

ET1100

ET1200

IP Core

Bit

Description

ECAT

PDI

Reset Value

31:0

one SyncManager asserts an PDI buffer

start event

r/-

NOTE: Register bits [31:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which

guarantees reading a consistent value.

Table 129: Register PDI Buffer Change Event Time (0x09FC:0x09FF)

ESC20

ET1100

ET1200

IP Core

Bit

Description

ECAT

PDI

Reset Value

31:0

one SyncManager asserts an PDI buffer

change event

r/-

NOTE: Register bits [31:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which

guarantees reading a consistent value.

1 2 ... 82 83 84 85 86 87 88 89 90 91 92 ... 97 98

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