Beckhoff EtherCAT Registers Section II Manual do Utilizador descarregar pdf (Página 88)

ESC specific registers (0x0E00:0x0EFF)

II-76 Slave Controller – Register Description

3.50 ESC specific registers (0x0E00:0x0EFF)

3.50.1 Power-On Values ET1200

Table 130: Register Power-On Values ET1200 (0x0E00)

ESC20

ET1100

ET1200

IP Core

Bit

Description

ECAT

PDI

Reset Value

1:0

Chip mode (MODE):

00: Port 0: EBUS, Port 1: EBUS, 18 bit PDI

01: Reserved

10: Port 0: MII, Port 1: EBUS, 8 bit PDI

11: Port 0: EBUS, Port 1: MII, 8 bit PDI

r/-

Depends on Hardware

configuration

3:2

CPU clock output (CLK_MODE):

00: Off – PDI[7] available as PDI port

01: PDI[7] = 25MHz

10: PDI[7] = 20MHz

11: PDI[7] = 10MHz

r/-

5:4

TX signal shift (C25_SHI):

00: MII TX signals shifted by 0°

01: MII TX signals shifted by 90°

10: MII TX signals shifted by 180°

11: MII TX signals shifted by 270°

r/-

CLK25 Output Enable (C25_ENA):

0: Disabled – PDI[6] available as PDI port

1: Enabled – PDI[6] = 25MHz (OSC)

NOTE: Only used in Chip mode 10 and 11

r/-

PHY Address Offset (PHYAD_OFF):

0: No PHY address offset

1: PHY address offset is 16

r/-

1 2 ... 83 84 85 86 87 88 89 90 91 92 93 ... 97 98

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